Three-dimensional semiconductor device

ABSTRACT

A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional application of U.S. patent applicationSer. No. 15/350,305, filed on Nov. 14, 2016, which claims priority under35 U.S.C. § 119 to Korean Patent Application No. 10-2015-0182062, filedon Dec. 18, 2015, in the Korean Intellectual Property Office, thedisclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

Example embodiments of the inventive concepts relate to athree-dimensional (3D) semiconductor device and, more particularly, to ahighly integrated 3D semiconductor memory device.

Semiconductor devices have been highly integrated in order to provideexcellent performance and low manufacturing costs. The integrationdensity of semiconductor devices directly affects the costs of thesemiconductor devices, thereby resulting in a demand of highlyintegrated semiconductor devices. The integration density of aconventional two-dimensional (2D) or planar semiconductor devices may bemainly determined by the area a unit memory cell occupies. Therefore,the integration density of the conventional 2D semiconductor devices maybe greatly affected by a technique of forming fine patterns. However,since, among other factors, extremely high-priced apparatuses are neededto form fine patterns, the integration density of 2D semiconductordevices continues to increase but is still limited. Three-dimensional(3D) semiconductor memory devices have been developed to overcome theabove limitations. 3D semiconductor memory devices may include memorycells three-dimensionally arranged.

SUMMARY

Example embodiments of the inventive concepts may provide athree-dimensional (3D) semiconductor device capable of improving anintegration density.

In an aspect, a 3D semiconductor device may include a substrateincluding a cell array region and a connection region, and a stackstructure extending from the cell array region to the connection region.The stack structure may include a first stack and a second stack on thefirst stack, and each of the first and second stacks may include a firstelectrode and a second electrode on the first electrode. A sidewall ofthe second electrode of the first stack may be horizontally spaced apartfrom a sidewall of the second electrode of the second stack by a firstdistance in the connection region. A sidewall of the first electrode maybe horizontally spaced apart from the sidewall of the second electrodeby a second distance in each of the first and second stacks. The seconddistance may be less than a half of the first distance.

In an aspect, a 3D semiconductor device may include a substrateincluding a cell array region and a connection region, and a pluralityof stacks vertically stacked on the substrate. Each of the stacks mayhave a pad portion disposed in the connection region, and each of thestacks may include a plurality of electrodes vertically stacked. Ends oftop surfaces of the pad portions of the stacks may be horizontallyspaced apart from each other by a first distance. In at least one of thepad portions of the stacks, a sidewall of an uppermost electrode may behorizontally spaced apart from a sidewall of a lowermost electrode by asecond distance. The second distance may be less than a half of thefirst distance.

In an aspect, a 3D semiconductor device may include a substrateincluding a cell array region and a connection region, a stack structureincluding a plurality of stacks vertically stacked on the substrate,each of the stacks having a pad portion disposed in the connectionregion, and contact plugs connected to the pad portions of the stacks,respectively. Each of the pad portions of the stacks may include aplurality of electrodes vertically stacked. In at least one of the padportions of the stacks, sidewalls of the electrodes may be horizontallyspaced apart from each other between the contact plugs adjacent to eachother.

In an aspect, a 3D semiconductor device may include a substrateincluding a cell array region and a connection region, and a stackstructure extending in one direction on the substrate. The stackstructure may include first electrodes and second electrodes that arealternately and vertically stacked on the substrate with an insulatinglayer interposed therebetween. Each of the first electrodes may have afirst end portion exposed by the second electrode disposed on each ofthe first electrodes in the connection region. Each of the secondelectrodes may have a second end portion exposed by the first electrodedisposed on each of the second electrodes in the connection region. Thefirst end portion of the first electrode may have a first width in theone direction, and the second end portion of the second electrode mayhave a second width in the one direction. The first width may be lessthan a half of the second width.

In example embodiments a 3D semiconductor device includes a substrateincluding a cell array region and a connection region, a stack structureincluding a plurality of stacks vertically stacked on the substrate,each of the stacks extending from the cell array region into theconnection region, wherein each subsequently higher stack extends alesser distance into the connection region than the stack below it; andeach stack includes a plurality of electrodes having sidewall and topsurfaces with an uppermost electrode extending into the connectionregion a lesser distance than any other electrode within the stack,wherein a line defined by the intersections of the sidewall and topsurfaces of the uppermost electrode in each stack forms an angle withthe substrate that is less than an angle formed by a line defined by theintersections of the sidewalls and tops of electrodes within a stack andthe substrate.

In example embodiments a 3D semiconductor device includes a plurality ofvertical structures penetrating the stacks in the cell array region anda data storage layer disposed between each of the vertical structuresand the stacks.

In example embodiments a 3D semiconductor device includes a verticalNAND (VNAND) device.

In example embodiments a semiconductor device includes a stackedstructure that includes two stepwise structures, the two stepwisestructures including a first stepwise structure defined by the steps ofindividual stacks within the stack structure and having the lesser anglewith the substrate associated with it and a second stepwise structuredefined by the steps of individual electrodes within individual stacksand having the greater angle with the substrate associated with it.

In example embodiments, a 3D semiconductor device includes a fillinginsulation layer formed on the substrate to cover the stack structure,conductive lines formed on top of the filling insulation layer andcontact plugs connecting the conductive lines to pads associatedelectrodes within each stack.

BRIEF DESCRIPTION OF THE DRAWINGS

The inventive concepts will become more apparent in view of the attacheddrawings and accompanying detailed description.

FIG. 1 is a cross-sectional view illustrating a three-dimensional (3D)semiconductor device according to some embodiments of the inventiveconcepts.

FIG. 2 is an enlarged view of a portion ‘A’ of FIG. 1.

FIGS. 3 to 7 are cross-sectional views illustrating portions of 3Dsemiconductor devices according to some embodiments of the inventiveconcepts.

FIG. 8 is a cross-sectional view illustrating a 3D semiconductor deviceaccording to some embodiments of the inventive concepts.

FIG. 9 is a cross-sectional view illustrating a 3D semiconductor deviceaccording to some embodiments of the inventive concepts.

FIG. 10 is an enlarged view of a portion ‘A’ of FIG. 9.

FIG. 11 is a cross-sectional view illustrating a 3D semiconductor deviceaccording to some embodiments of the inventive concepts.

FIG. 12 is a cross-sectional view illustrating a 3D semiconductor deviceaccording to some embodiments of the inventive concepts.

FIG. 13 is an enlarged view of a portion ‘A’ of FIG. 12.

FIG. 14 is a cross-sectional view illustrating a 3D semiconductor deviceaccording to some embodiments of the inventive concepts.

FIG. 15 is an enlarged view of a portion ‘A’ of FIG. 14.

FIG. 16 is a cross-sectional view illustrating a 3D semiconductor deviceaccording to some embodiments of the inventive concepts.

FIG. 17 is an enlarged view of a portion ‘A’ of FIG. 16.

FIG. 18 is a cross-sectional view illustrating a 3D semiconductor deviceaccording to some embodiments of the inventive concepts.

FIG. 19 is an enlarged view of a portion ‘A’ of FIG. 18.

FIGS. 20 and 21 are cross-sectional views illustrating 3D semiconductordevices according to some embodiments of the inventive concepts.

FIGS. 22 and 23 are cross-sectional views illustrating 3D semiconductordevices according to some embodiments of the inventive concepts.

FIGS. 24 to 28 are cross-sectional views illustrating a method offorming a stack structure of a 3D semiconductor device according to someembodiments of the inventive concepts.

FIG. 29 is a schematic block diagram illustrating a 3D semiconductormemory device according to some embodiments of the inventive concepts.

FIG. 30 is a plan view illustrating a 3D semiconductor memory deviceaccording to some embodiments of the inventive concepts.

FIG. 31 is a cross-sectional view taken along a line I-I′ of FIG. 30 toillustrate a 3D semiconductor memory device according to someembodiments of the inventive concepts.

FIG. 32 is a schematic block diagram illustrating a 3D semiconductormemory device according to some embodiments of the inventive concepts.

FIG. 33 is a cross-sectional view illustrating the 3D semiconductormemory device according to some embodiments of the inventive concepts,which is described with reference to FIG. 32.

DETAILED DESCRIPTION

FIG. 1 is a cross-sectional view illustrating a three-dimensional (3D)semiconductor device according to example embodiments of the inventiveconcepts. FIG. 2 is an enlarged view of a portion ‘A’ of FIG. 1.

An integrated circuit including a vertically stacked structure, such asa VNAND device, may include a cell array region CAR and connectionregion CNR. In example embodiments a stack structure ST includesplurality of stacks STR that extend from the cell array region CAR intothe connection region CNR. Each subsequently higher stack STR (that is,“higher” in the sense that it is farther from the substrate 10 uponwhich the stack resides) extends a lesser distance into connectionregion CNR than the stack STR below it. Each stack STR includes aplurality of electrodes, with upper electrode(s) extending intoconnection region CNR a lesser distance than the electrode below it. Forexample, in an embodiment in which each stack STR includes twoelectrodes EL1 and EL2, an upper and a lower electrode, the upperelectrode EL2 extends into the connection region less than the lowerelectrode EL1.

A line drawn along the intersections of the sidewalls and tops of theshortest of the electrodes in the different stacks within a stackstructure forms an angle with the substrate that is different from (forexample, less than) the angle between the substrate and a line drawnalong the intersections of the sidewalls and tops of electrodes within astack. For example, in an example embodiment in which each stack STRincludes two electrodes (EL2 (upper) and EL1 (lower)), each of which maybe viewed as tread (top surface) and riser (sidewall) of steps in thestack STR, and five stacks STR within a stack structure ST, a line drawnalong the intersections of the sidewalls and tops of the shortest of theelectrodes in the different stacks (EL2) within a stack structure STforms an angle with the substrate that is different from (for example,less than) the angle between the substrate 10 (or the top electrode inthe immediately lower stack) and a line drawn along the intersections ofthe sidewalls and tops of electrodes within a stack (that is, along theintersections of the sidewalls and tops of electrodes EL2 and EL1). Thesidewalls of electrodes may be slanted at an angle with the substrate 10in example embodiments.

The stacked structure ST may be viewed as two stepwise structures: afirst stepwise structure defined by the “steps” of individual stackswithin the stack structure (having the lesser angle associated with it)and a second stepwise structure defined by the “steps” of individualelectrodes within individual stacks (having the greater angle associatedwith it).

A filling insulation layer 110 may be formed on the substrate 10 tocover the stack structure ST, with conductive lines CL formed on top.Contact plugs PLG may connect conductive lines CL to pads PAD disposedon, or constituted by, the uppermost of electrodes (for example, EL2)within each stack STR. In example embodiments in accordance withprinciples of inventive concepts, the second stepwise structure ofindividual stacks STR may effect better filling of the fillinginsulation layer 110, without voids (or air space).

In example embodiments, the distance D2 between the ends of electrodeswithin a stack STR may be less than the distance D1 betweencorresponding electrodes (EL2 s, for example) within different stacksSTR. The distance P1 between top and bottom electrodes within a stackSTR may be greater than the distance P2 between, or thickness of,electrodes within a stack STR.

Referring to FIGS. 1 and 2, a substrate 10 may include a cell arrayregion CAR and a connection region CNR. A stack structure ST may bedisposed on the substrate 10 of the cell array region CAR and theconnection region CNR and may extend in one direction away from the cellarray region CAR. The stack structure ST may have a stepwise structureon the substrate 10 of the connection region CNR. In other words, aheight of the stack structure ST of the connection region CNR may bereduced stepwise as a horizontal distance from the cell array region CARinto the connection region CNR increases. That is, in exampleembodiments the stack structure ST extends into the connection regionCNR with the extension into the connection region CNR decreasing witheach stack structure STR subsequently layered over a preceding stacksSTR.

The stack structure ST may include a plurality of stacks STR verticallystacked on the substrate 10. Each of the stacks STR may include aplurality of electrodes EL1 and EL2 vertically stacked and insulatinglayers ILD disposed between the electrodes EL1 and EL2. The electrodesEL1 and EL2 may be formed of a conductive material (e.g., a dopedsemiconductor material or a metal). In some embodiments, each of thestacks STR may include a first electrode ELL and a second electrode EL2disposed on the first electrode EL1.

In example embodiments, each of the stacks STR may include a pad portionPAD in the connection region CNR. In example embodiments, end portionsEP1 and EP2 of the first and second electrodes EL1 and EL2 of each ofthe stacks STR may constitute the pad portion PAD in the connectionregion CNR. In example embodiments, each of the first electrodes EL1 mayhave a first end portion EP1 exposed (that is, left uncovered) by thesecond electrode EL2 disposed thereon, and each of the second electrodesEL2 may have a second end portion EP2 exposed by the first electrode EL1disposed thereon. Each of the pad portions PAD may include the first endportion EP1 of the first electrode ELL and a second end portion EP2 thesecond electrode EL2. As illustrated in FIG. 2, the first end portionEP1 may have a first width W1, and the second end portion EP2 may have asecond width W2. In example embodiments, the first width W1 may be lessthan half of the second width W2.

Lengths of the stacks STR may be sequentially reduced as a height fromthe substrate 10 increases. As a result, the pad portion PAD of theupper one of the stacks STR vertically adjacent to each other may exposethe pad portion PAD of the lower one of the stacks STR verticallyadjacent to each other. In other words, the pad portions PAD of thestacks STR may constitute the stepwise structure (that is, the “risersand treads”) on the substrate 10 in the connection region CNR.

In other words, the stack structure ST including the plurality of stacksSTR may include a plurality of the pad portions PAD that are disposed atpositions vertically and horizontally different from each other in theconnection region CNR. Ends of top surfaces of the pad portions PAD maybe horizontally spaced apart from each other at equal distances. Inexample embodiments, each of the pad portions PAD may include theplurality of electrodes sequentially stacked.

In example embodiments, the ends of the top surfaces of the pad portionsPAD of stack structure ST may be horizontally spaced apart from eachother by a first distance D1, and the top surfaces of the pad portionsPAD may be vertically spaced apart from each other by a first verticalpitch P1, as illustrated in FIG. 2. In example embodiments, the firstvertical pitch P1 refers to a height difference between the top surfacesof the pad portions PAD vertically adjacent to each other. The firstvertical pitch P1 may be changed according to the number of theelectrodes included in each of the pad portions PAD. In someembodiments, the first vertical pitch P1 may be equal to or greater thantwice a second vertical pitch P2 between a top surface of the firstelectrode EL1 and a top surface of the second electrode EL2.

In example embodiments, contact plugs PLG may be connected to the padportions PAD of the stack structure ST, respectively. Each of thecontact plugs PLG may be in contact with the uppermost electrode (e.g.,the second electrode EL2) of each of the pad portions PAD. In each ofthe pad portions PAD, a sidewall of the lowermost electrode (e.g., thefirst electrode EL1) may be horizontally spaced apart from a sidewall ofthe uppermost electrode (e.g., the second electrode EL2). The sidewallsof the first and second electrodes EL1 and EL2 of each of the padportions PAD may be disposed between the contact plugs PLG adjacent toeach other.

In example embodiments, in each of the pad portions PAD, the secondelectrode EL2 corresponding to the uppermost electrode may be in contactwith the contact plug PLG, and the sidewall of the first electrode EL1corresponding to the lowermost electrode may be horizontally spacedapart from the sidewall of the second electrode EL2. As illustrated inFIG. 2, a second distance D2 corresponding to a horizontal distancebetween the sidewalls of the first and second electrodes EL1 and EL2 maybe less than about a half of the first distance D1. In addition, thesecond distance D2 may be less than a width W of the contact plug PLG.

Due to the pad portions PAD, the stack structure ST may have a sidewallprofile of a first stepwise structure. Because the sidewalls of thefirst and second electrodes EL1 and EL2 of each of the pad portions PADare horizontally spaced apart from each other, each of the pad portionsPAD may have a sidewall profile of a second stepwise structure. Thefirst stepwise structure may have a first inclination angle θ1 withrespect to a top surface of the substrate 10, and the first inclinationangle θ1 may be smaller than 90 degrees. The second stepwise structuremay have a second inclination angle θ2 with respect to the top surfaceof the substrate 10, and the second inclination angle θ2 may be greaterthan the first inclination angle θ1 and smaller than 90 degrees.

A filling insulation layer 110 may be disposed on the substrate 10 tocover the stack structure ST and may have a planarized top surface.Conductive lines CL may be disposed on the filling insulation layer 110of the connection region CNR and may be connected to the contact plugsPLG, respectively.

Due to a height difference between the stack structure ST of the cellarray region CAR and the stack structure ST of the connection regionCNR, the filling insulation layer 110 may become progressively thickeras a horizontal distance from the cell array region CAR increases. Thefilling insulation layer 110 may fill spaces SR (hereinafter, referredto as “stepped regions SR”), each of which is defined between the padportions PAD vertically adjacent to each other.

In example embodiments, as the height of the stack structure ST of thecell array region CAR (i.e., the number of the stacked electrodes EL1and EL2) increases, the number of the electrodes EL1 and EL2 of each ofthe pad portions PAD may also increase. Because each of the pad portionsPAD has the sidewall profile of the second stepwise structure having thesecond inclination angle θ2 by the electrodes EL1 and EL2 thereof, thefilling insulation layer 110 may easily fill the stepped regions SR eventhough the first vertical pitch P1 of the pad portions PAD increases.

FIGS. 3 to 7 are cross-sectional views illustrating portions of stackstructures of 3D semiconductor devices according to example embodimentsof the inventive concepts. The descriptions to the same elements ortechnical features as in the embodiment of FIGS. 1 and 2 will be omittedor mentioned only briefly for the purpose of ease and convenience inexplanation.

Referring to FIGS. 3 to 7, a stack structure ST may include a pluralityof stacks STR vertically stacked, and each of the stacks STR may includea pad portion PAD disposed in the connection region CNR. Thus, the stackstructure ST may include the pad portions PAD disposed at positionsvertically and horizontally different from each other. In exampleembodiments, ends of top surfaces of the pad portions PAD verticallyadjacent to each other may be horizontally spaced apart from each otherby a first distance D1, and the top surfaces of the adjacent padportions PAD may be vertically spaced apart from each other by a firstvertical pitch P1.

In example embodiments, each of the stacks STR may include a pluralityof electrodes EL1, EL2, EL3, and EL4 vertically stacked, and a secondvertical pitch P2 of the electrodes EL1, EL2, EL3, and EL4 may besmaller than a half of the first vertical pitch P1. In some embodiments,each of the stacks STR may include first, second, third, and fourthelectrodes EL1, EL2, EL3, and EL4 sequentially stacked, and each of thepad portions PAD may include end portions of the first to fourthelectrodes EL1, EL2, EL3, and EL4. The first to fourth electrodes EL1,EL2, EL3, and EL4 may have substantially the same thickness and may bestacked at equal second vertical pitches P2. In each of the pad portionsPAD, the fourth electrode EL4 corresponding to the uppermost electrodemay be in contact with the contact plug PLG, and a sidewall of the firstelectrode EL1 corresponding to the lowermost electrode may behorizontally spaced apart from a sidewall of the fourth electrode EL4 bya second distance D2. In example embodiments, the second distance D2 maybe less than about a half of the first distance D1.

This stack structure ST may have a first stepwise structure formed bythe pad portions PAD and a second stepwise structure formed by the firstto fourth electrodes EL1, EL2, EL3, and EL4 of each of the pad portionsPAD. In example embodiments, the first stepwise structure may have afirst inclination angle θ1 and the second stepwise structure may have asecond inclination angle θ2, different from the first inclination angleθ1, as described with reference to FIGS. 1 and 2.

Referring to FIGS. 3 and 4, sidewalls of the second and third electrodesEL2 and EL3 may be horizontally spaced apart from each other between thesidewalls of the first and fourth electrodes EL1 and EL4. In exampleembodiments, the sidewalls of the first to fourth electrodes EL1, EL2,EL3, and EL4 may be substantially perpendicular to top surfaces of thefirst to fourth electrodes EL1, EL2, EL3, and EL4. Alternatively, asillustrated in FIG. 4, the first to fourth electrodes EL1, EL2, EL3, andEL4 may respectively have sidewalls inclined to the top surfaces of thefirst to fourth electrodes EL1, EL2, EL3, and EL4.

Referring to FIG. 5, a sidewall of the third electrode EL3 disposedunder the uppermost fourth electrode EL4 may be aligned with thesidewall of the uppermost fourth electrode EL4. In addition, a sidewallof the second electrode EL2 disposed on the lowermost first electrodeEL1 may be aligned with the sidewall of the lowermost first electrodeEL1.

In example embodiments, as illustrated in FIG. 6, sidewalls of thesecond and third electrodes EL2 and EL3 may be aligned with the sidewallof the lowermost first electrode EL1. In other example embodiments, asillustrated in FIG. 7, sidewalls of the second and third electrodes EL2and EL3 may be aligned with the sidewall of the uppermost fourthelectrode EL4.

FIG. 8 is a cross-sectional view illustrating a 3D semiconductor deviceaccording to example embodiments of the inventive concepts.

Referring to FIG. 8, a substrate 10 may include a first connectionregion CNR1, a second connection region CNR2, and a cell array regionCAR disposed between the first and second connection regions CNR1 andCNR2. A stack structure ST may be disposed on the substrate 10. Thestack structure ST may include a plurality of stacks STR verticallystacked on the substrate 10. The stack structure ST may extend from thecell array region CAR into the first and second connection regions CNR1and CNR2 and may have stepwise structures in the first and secondconnection regions CNR1 and CNR2. In other words, lengths of the stacksSTR may sequentially decrease as a vertical distance from the substrate10 increases.

In example embodiments, each of the stacks STR may include electrodesEL1 and EL2 vertically stacked and insulating layers ILD disposedbetween the electrodes EL1 and EL2. In example embodiments, each of thestacks STR may include first and second electrodes EL1 and EL2 and theinsulating layer ILD disposed between the first and second electrodesEL1 and EL2. In other words, the stack structure ST including theplurality of stacks STR may include the first electrodes EL1 and thesecond electrodes EL2, which are alternately and repeatedly stacked.Each of the first electrodes EL1 may have first end portionsrespectively disposed in the first and second connection regions CNR1and CNR2, and each of the second electrodes EL2 may have second endportions respectively disposed in the first and second connectionregions CNR1 and CNR2.

According to some example embodiments of the inventive concepts, thestack structure ST may include first pad portions PAD1 that are disposedat positions vertically different from each other in the firstconnection region CNR1. Ends of top surfaces of the first pad portionsPAD1 may be horizontally spaced apart from each other at equaldistances. In addition, the stack structure ST may include second padportions PAD2 that are disposed at positions vertically different fromeach other in the second connection region CNR2. Ends of top surfaces ofthe second pad portions PAD2 may be horizontally spaced apart from eachother at equal distances.

In example embodiments, each of the first and second pad portions PAD1and PAD2 may include the end portions of the first and second electrodesEL1 and EL2, which are stacked. In detail, each of the first padportions PAD1 may include the first end portion of the first electrodeEL1 and the second end portion of the second electrode EL2 disposed onthe first electrode ELL which are disposed in the first connectionregion CNR1. Each of the second pad portions PAD2 may include the secondend portion of the second electrode EL2 and the first end portion of thefirst electrode EL1 disposed on the second electrode EL2, which aredisposed in the second connection region CNR2.

In example embodiments, the ends of the top surfaces of the first padportions PAD1 adjacent to each other may be horizontally spaced apartfrom each other by a first distance D1 in the first connection regionCNR1. The top surfaces of the first pad portions PAD1 adjacent to eachother may be vertically spaced apart from each other by a first verticalpitch (P1 of FIG. 2) in the first connection region CNR1. The firstvertical pitch P1 may be equal to or greater than twice a vertical pitch(P2 of FIG. 2) of the first and second electrodes EL1 and EL2. Likewise,the ends of the top surfaces of the second pad portions PAD2 adjacent toeach other may be horizontally spaced apart from each other by a thirddistance D3 in the second connection region CNR2. The top surfaces ofthe second pad portions PAD2 adjacent to each other may be verticallyspaced apart from each other by the first vertical pitch (P1 of FIG. 1)in the second connection region CNR2. In some embodiments, the thirddistance D3 may be equal to the first distance D1. Alternatively, thethird distance D3 may be different from the first distance D1. Inaddition, the second pad portions PAD2 may be disposed at differentlevels from the first pad portions PAD1. Vertical thicknesses of thefirst pad portions PAD1 may be substantially equal to each other. Thevertical thickness of at least one of the second pad portions PAD2 maybe different from vertical thicknesses of others of the second padportions PAD2. For example, the vertical thickness of the lowermost oneof the second pad portions PAD2 may be smaller than those of others ofthe second pad portions PAD2.

In example embodiments, first contact plugs PLG1 may be connected to thesecond electrodes EL2 of the first pad portions PAD1, respectively, andsecond contact plugs PLG2 may be connected to the first electrodes EL1of the second pad portions PAD2, respectively.

In the first connection region CNR1, the ends of the top surfaces of thefirst pad portions PAD1 may be horizontally spaced apart from each otherby the first distance D1 as described above. In example embodiments, thefirst distance D1 may be substantially equal to a horizontal distancebetween sidewalls of the first electrodes EL1 adjacent to each other anda horizontal distance between sidewalls of the second electrodes EL2adjacent to each other in the first connection region CNR1.

In each of the first pad portions PAD1, the sidewall of the secondelectrode EL2 and the sidewall of the first electrode EL1 may bedisposed at positions horizontally different from each other, and thesidewall of the second electrode EL2 may be horizontally spaced apartfrom the sidewall of the first electrode EL1 by a second distance D2. Inexample embodiments, the second distance D2 may be less than a half ofthe first distance D1 corresponding to a horizontal distance between theends of the top surfaces of the first pad portions PAD1 adjacent to eachother. In addition, the second distance D2 may be less than the width ofthe first contact plug PLG1. The sidewalls of the first and secondelectrodes EL1 and EL2 of each of the first pad portions PAD1 may bedisposed between the first contact plugs PLG1 adjacent to each other.

In the second connection region CNR2, the ends of the top surfaces ofthe second pad portions PAD2 may be horizontally spaced apart from eachother by the third distance D3 as described above. In exampleembodiments, the third distance D3 may be substantially equal to ahorizontal distance between sidewalls of the first electrodes EL1adjacent to each other and a horizontal distance between sidewalls ofthe second electrodes EL2 adjacent to each other in the secondconnection region CNR2.

In each of the second pad portions PAD2, the sidewall of the firstelectrode EL1 and the sidewall of the second electrode EL2 may bedisposed at positions horizontally different from each other, and thesidewall of the second electrode EL2 may be horizontally spaced apartfrom the sidewall of the first electrode EL1 by a fourth distance D4. Inexample embodiments, the fourth distance D4 may be less than a half ofthe third distance D3 corresponding to a horizontal distance between theends of the top surfaces of the second pad portions PAD2 adjacent toeach other. In addition, the fourth distance D4 may be less than a widthof the second contact plug PLG2. In example embodiments, the fourthdistance D4 may be substantially equal to the second distance D2.Alternatively, the fourth distance D4 may be different from the seconddistance D2. The sidewalls of the first and second electrodes EL1 andEL2 of each of the second pad portions PAD2 may be disposed between thesecond contact plugs PLG2 adjacent to each other.

The stack structure ST may have a first stepwise structure realized bythe first pad portions PAD1 in the first connection region CNR1, andeach of the first pad portions PAD1 may have a second stepwise structurerealized by the first and second electrodes EL1 and EL2 includedtherein. The first stepwise structure may have a first inclination angleθ1 with respect to a top surface of the substrate 10, and the firstinclination angle θ1 may be smaller than 90 degrees. The second stepwisestructure may have a second inclination angle θ2 with respect to the topsurface of the substrate 10, and the second inclination angle θ2 may begreater than the first inclination angle θ1 and smaller than 90 degrees.The stack structure ST may also include the first and second stepwisestructures in the second connection region CNR2.

A filling insulation layer 110 may be disposed on an entire top surfaceof the substrate 10 to cover the stack structure ST and may have aplanarized top surface. First conductive lines CL1 may be disposed onthe filling insulation layer 110 of the first connection region CNR1 soas to be connected to the first contact plugs PLG1, respectively, andsecond conductive lines CL2 may be disposed on the filling insulationlayer 110 of the second connection region CNR2 so as to be connected tothe second contact plugs PLG2, respectively.

FIG. 9 is a cross-sectional view illustrating a 3D semiconductor deviceaccording to example embodiments of the inventive concepts. FIG. 10 isan enlarged view of a portion ‘A’ of FIG. 9. In the embodiment of FIGS.9 and 10, the descriptions of the same elements or technical features asin the embodiment of FIG. 8 will be omitted or only mentioned brieflyfor the purpose of ease and convenience in explanation.

Referring to FIG. 9, a stack structure ST may include a plurality ofstacks STR vertically stacked, and each of the stacks STR may includefirst and second electrodes EL1 and EL2 vertically stacked.

The stack structure ST may include first pad portions PAD1 that aredisposed at positions horizontally and vertically different from eachother in a first connection region CNR1. In addition, the stackstructure ST may include second pad portions PAD2 that are disposed atpositions horizontally and vertically different from each other in asecond connection region CNR2.

In example embodiments, ends of top surfaces of the first pad portionsPAD1 of stack structure ST may be horizontally spaced apart from eachother by a first distance D1, and the top surfaces of the first padportions PAD1 may be vertically spaced apart from each other by a firstvertical pitch P1, as illustrated in FIG. 10. Here, the first verticalpitch P1 may be equal to or greater than about twice a height differenceP2 (or a second vertical pitch P2) of the first and second electrodesEL1 and EL2. Likewise, ends of top surfaces of the second pad portionsPAD2 may be horizontally spaced apart from each other by a thirddistance in the second connection region CNR2. The top surfaces of thesecond pad portions PAD2 may be vertically spaced apart from each otherby the first vertical pitch P1 in the second connection region CNR2.

In example embodiments, first contact plugs PLG1 may be connected to thesecond electrodes EL2 of the first pad portions PAD1, respectively, andsecond contact plugs PLG2 may be connected to the first electrodes EL1of the second pad portions PAD2, respectively.

In example embodiments, in at least one of the first pad portions ELLsidewalls of the first and second electrodes EL1 and EL2 may be alignedwith each other. In addition, in at least another of the first padportions PAD1, a sidewall of the second electrode EL2 and a sidewall ofthe first electrode EL1 may be disposed at positions vertically andhorizontally different from each other. In example embodiments, a seconddistance D2 corresponding to a horizontal distance between the sidewallsof the first and second electrodes EL1 and EL2 may be less than a halfof the first distance D1 corresponding to the horizontal distancebetween the ends of the top surfaces of the first pad portions PAD1.Likewise, sidewalls of the first and second electrodes EL1 and EL2 of atleast one of the second pad portions PAD2 may be aligned with eachother, and sidewalls of the first and second electrodes EL1 and EL2 ofat least another of the second pad portions PAD2 may be disposed atpositions vertically and horizontally different from each other.

The sidewalls of the first and second electrodes EL1 and EL2 of each ofthe first pad portions PAD1 may be disposed between the first contactplugs PLG1 adjacent to each other, and the sidewalls of the first andsecond electrodes EL1 and EL2 of each of the second pad portions PAD2may be disposed between the second contact plugs PLG2 adjacent to eachother.

According to the present example embodiment, the stack structure ST mayhave the first stepwise structure realized by the first pad portionsPAD1 in the first connection region CNR1, and at least one of the firstpad portions PAD1 may have the second stepwise structure realized by thefirst and second electrodes EL1 and EL2 vertically adjacent to eachother. The first and second stepwise structures may also be provided inthe second connection region CNR2.

FIG. 11 is a cross-sectional view illustrating a 3D semiconductor deviceaccording to example embodiments of the inventive concepts. In thepresent example embodiment, the descriptions of the same elements ortechnical features as in the embodiment of FIG. 8 will be omitted oronly mentioned briefly for the purpose of ease and convenience inexplanation.

Referring to FIG. 11, as described above, the stack structure ST mayinclude first pad portions PAD1 of the first connection region CNR1 andsecond pad portions PAD2 of the second connection region CNR2. Asdescribed above, the first pad portions PAD1 may be disposed atpositions horizontally and vertically different from each other in thefirst connection region CNR1, and the second pad portions PAD2 may bedisposed at positions horizontally and vertically different from eachother in the second connection region CNR2.

Each of the first and second pad portions PAD1 and PAD2 may includefirst and second electrodes EL1 and EL2 vertically adjacent to eachother, and the first and second electrodes EL1 and EL2 may havesidewalls inclined to top surfaces of the first and second electrodesEL1 and EL2. In other words, each of the first and second pad portionsPAD1 and PAD2 may have an inclined sidewall profile.

In example embodiments, the stack structure ST may have a first stepwisestructure realized by the first pad portions PAD1 in the firstconnection region CNR1, and each of the first pad portions PAD1 may havethe inclined sidewall profile. Likewise, the stack structure ST may havethe first stepwise structure realized by the second pad portions PAD2 inthe second connection region CNR2, and each of the second pad portionsPAD2 may have the inclined sidewall profile. In example embodiments, thefirst stepwise structure may have a first inclination angle (see 01 ofFIG. 3) smaller than 90 degrees with respect to the top surface of thesubstrate 10, and the sidewall of each of the pad portions PAD1 and PAD2may have a second inclination angle (see 02 of FIG. 3) that is greaterthan the first inclination angle (see 01 of FIG. 3) and smaller than 90degrees.

FIG. 12 is a cross-sectional view illustrating a 3D semiconductor deviceaccording to example embodiments of the inventive concepts, and FIG. 13is an enlarged view of a portion ‘A’ of FIG. 12. In the present exampleembodiment, the descriptions of the same elements or technical featuresas in the embodiment of FIG. 8 will be omitted or mentioned only brieflyfor the purpose of ease and convenience in explanation.

Referring to FIGS. 12 and 13, a stack structure ST may be disposed on asubstrate 10 including first and second connection regions CNR1 and CNR2and a cell array region CAR disposed between the first and secondconnection regions CNR1 and CNR2. The stack structure ST may include aplurality of stacks STR stacked on the substrate 10, and lengths of thestacks STR may be sequentially reduced as a distance from the substrate10 increases. In example embodiments, each of the stacks STR may includea first electrode ELL a second electrode EL2, and a third electrode EL3which are sequentially stacked. Each of the first to third electrodesELL EL2, and EL3 may have end portions respectively disposed in thefirst and second connection regions CNR1 and CNR2.

The stack structure ST may include first pad portions PAD1 which aredisposed at positions horizontally and vertically different from eachother in a first connection region CNR1. In addition, the stackstructure ST may also include second pad portions PAD2 which aredisposed at positions horizontally and vertically different from eachother in a second connection region CNR2. The stack structure ST mayhave stepwise sidewall profiles by the first and second pad portionsPAD1 and PAD2 in the first and second connection regions CNR1 and CNR2.

In the first connection region CNR1, ends of top surfaces of the firstpad portions PAD1 adjacent to each other may be horizontally spacedapart from each other by a first distance D1 and may be disposed atlevels different from each other based on a top surface of the substrate10. Likewise, in the second connection region CNR2, ends of top surfacesof the second pad portions PAD2 adjacent to each other may behorizontally spaced apart from each other by a third distance D3 and maybe disposed at levels different from each other based on the top surfaceof the substrate 10. The first pad portions PAD1 may be disposed atdifferent levels from the second pad portions PAD2 based on the topsurface of the substrate 10.

In example embodiments, at least one of the first pad portions PAD1 mayhave the end portions of the first to third electrodes ELL EL2, and EL3vertically adjacent to each other, and at least one of the second padportions PAD2 may have the end portions of the first to third electrodesELL EL2, and EL3 vertically adjacent to each other. The lowermost one ofthe first pad portions PAD1 may have the end portions of the first andsecond electrodes EL1 and EL2 vertically stacked. The lowermost one ofthe second pad portions PAD2 may have the end portion of the lowermostfirst electrode EL1 of the stack structure ST.

In example embodiments, in each of the first pad portions PAD1, theuppermost electrode may be in contact with the first contact plug PLG1and a sidewall of the lowermost electrode may be horizontally spacedapart from a sidewall of the uppermost electrode. In exampleembodiments, a second distance D2 corresponding to a horizontal distancebetween the sidewalls of the uppermost and lowermost electrodes may beless than about a half of the first distance D1 corresponding to thehorizontal distance between the ends of the top surfaces of the firstpad portions PAD1.

In example embodiments, in at least one of the first pad portions PAD1,the second electrode EL2 may correspond to the uppermost electrode, thethird electrode EL3 may correspond to the lowermost electrode, and thefirst electrode EL1 may be disposed between the second and thirdelectrodes EL2 and EL3. In example embodiments, the end portion of thefirst electrode EL1 may be exposed by the second electrode EL2, and theend portion of the third electrode EL3 may be exposed by the firstelectrode EL1.

The end portion of the second electrode EL2 corresponding to theuppermost electrode may be in contact with the first contact plug PLG1.The second distance D2 corresponding to a horizontal distance betweenthe sidewall of the lowermost third electrode EL3 and the sidewall ofthe uppermost second electrode EL2 may be less than a half of the firstdistance D1 corresponding to the horizontal distance between the ends ofthe top surfaces of the first pad portions PAD1. The sidewall of thefirst electrode EL1 disposed between the second and third electrodes EL2and EL3 may be horizontally spaced apart from the sidewalls of thesecond and third electrodes EL2 and EL3.

In example embodiments, in each of the second pad portions PAD2, theuppermost electrode may be in contact with the second contact plug PLG2and a sidewall of the lowermost electrode may be horizontally spacedapart from a sidewall of the uppermost electrode. In exampleembodiments, a fourth distance D4 corresponding to a horizontal distancebetween the sidewalls of the uppermost and lowermost electrodes of eachof the second pad portions PAD2 may be less than about a half of thethird distance D3.

In example embodiments, in at least one of the second pad portions PAD2,the first electrode EL1 may correspond to the uppermost electrode andthe second electrode EL2 may correspond to the lowermost electrode. Inaddition, the third electrode EL3 may be disposed between the first andsecond electrodes EL1 and EL2 in at last one of the second pad portionsPAD2. In example embodiments, the end portion of the third electrode EL3may be exposed by the first electrode EL1, and the end portion of thesecond electrode EL2 may be exposed by the third electrode EL3.

The second contact plug PLG2 may be connected to the first electrode EL1corresponding to the uppermost electrode. The fourth distance D4 betweenthe sidewalls of the uppermost second electrode EL1 and the lowermostsecond electrode EL2 may be less than a half of the third distance D3.In addition, the fourth distance D4 may be less than a width of thesecond contact plug PLG2. The sidewall of the third electrode EL3disposed between the first and second electrodes EL1 and EL2 may behorizontally spaced apart from the sidewalls of the first and secondelectrodes EL1 and EL2.

The stack structure ST may have a first stepwise structure realized bythe first pad portions PAD1 in the first connection region CNR1, andeach of the first pad portions PAD1 may have a second stepwise structurerealized by the first to third electrodes EL1, EL2, and EL3 verticallyadjacent to each other. The first stepwise structure may have a firstinclination angle θ1 smaller than 90 degrees with respect to the topsurface of the substrate 10, and the second stepwise structure may havea second inclination angle θ2 which is greater than the firstinclination angle θ1 and smaller than 90 degrees. The stack structure STmay also include the first and second stepwise structures in the secondconnection region CNR2.

When the filling insulation layer 110 is deposited in the stepped regionbetween the first pad portions PAD1 vertically adjacent to each other,the stepped region may be easily filled with the filling insulationlayer 110 due to the second stepwise structures of the first padportions PAD1.

FIG. 14 is a cross-sectional view illustrating a 3D semiconductor deviceaccording to example embodiments of the inventive concepts, and FIG. 15is an enlarged view of a portion ‘A’ of FIG. 14. In the present exampleembodiment, the descriptions of the same elements or technical featuresas in the embodiment of FIGS. 12 and 13 will be omitted or mentionedonly briefly for the purpose of ease and convenience in explanation.

Referring to FIGS. 14 and 15, a stack structure ST may include aplurality of stacks STR stacked on a substrate 10, and each of thestacks STR may include a first electrode ELL a second electrode EL2, anda third electrode EL3 which are sequentially stacked.

First pad portions PAD1 of the stack structure ST may be disposed on thesubstrate 10 of the first connection region CNR1, and second padportions PAD2 of the stack structure ST may be disposed on the substrate10 of the second connection region CNR2. As described above, each of thefirst and second pad portions PAD1 and PAD2 may include end portions ofthe first to third electrodes EL1 to EL3 vertically adjacent to eachother.

In example embodiments, in at least one of the first pad portions PAD1,the second electrode EL2 may correspond to the uppermost electrode andthe third electrode EL3 may correspond to the lowermost electrode. Inaddition, the first electrode EL1 may be disposed between the second andthird electrodes EL2 and EL3 in the at last one of the first padportions PAD1. In at least one of the second pad portions PAD2, thefirst electrode EL1 may correspond to the uppermost electrode and thesecond electrode EL2 may correspond to the lowermost electrode. Inaddition, the third electrode EL3 may be disposed between the first andsecond electrodes EL1 and EL2 in the at last one of the second padportions PAD2.

In these example embodiments, first contact plugs PlG1 may be connectedto the second electrodes EL2 of the first pad portions PAD1 in firstconnection region CNR1, respectively, and second contact plugs PlG2 maybe connected to the first electrodes EL1 of the second pad portions PAD2in the second connection region CNR2, respectively.

In addition, in at least one of the first pad portions PAD1, a sidewallof the second electrode EL2 corresponding to the uppermost electrode maybe horizontally spaced apart from a sidewall of the third electrode EL3corresponding to the lowermost electrode. In example embodiments, thesecond distance D2 between the sidewalls of the second and thirdelectrodes EL2 and EL3 may be less than a half of the first distance D1.In addition, the sidewall of the first electrode EL1 disposed betweenthe second and third electrodes EL2 and EL3 may be disposed between thesidewalls of the second and third electrodes EL2 and EL3 when viewedfrom a plan view.

In example embodiments, in another of the first pad portions PAD1,sidewalls of the first to third electrodes EL1, EL2, and EL3 may bevertically aligned with each other. In other words, the sidewalls of thefirst to third electrodes EL1, EL2, and EL3 of the another first padportion PAD1 may be vertically coplanar with each other.

Likewise, in at least one of the second pad portions PAD2, a sidewall ofthe first electrode EL1 corresponding to the uppermost electrode may behorizontally spaced apart from a sidewall of the second electrode EL2corresponding to the lowermost electrode. In example embodiments, thehorizontal distance between the sidewalls of the first and secondelectrodes EL1 and EL2 may be less than a half of the horizontaldistance between the ends of the top surfaces of the second pad portionsPAD2. In addition, the sidewall of the third electrode EL3 disposedbetween the first and second electrodes EL1 and EL2 may be disposedbetween the sidewalls of the first and second electrodes EL1 and EL2when viewed from a plan view.

In example embodiments, in another of the second pad portions PAD2,sidewalls of the first to third electrodes EL1, EL2, and EL3 may bevertically aligned with each other. In other words, the sidewalls of thefirst to third electrodes EL1, EL2, and EL3 of the another second padportion PAD2 may be vertically coplanar with each other.

FIG. 16 is a cross-sectional view illustrating a 3D semiconductor deviceaccording to example embodiments of the inventive concepts, and FIG. 17is an enlarged view of a portion ‘A’ of FIG. 16. In the present exampleembodiment, the descriptions of the same elements or technical featuresas in the embodiment of FIGS. 12 and 13 will be omitted or mentionedonly briefly for the purpose of ease and convenience in explanation.

Referring to FIGS. 16 and 17, each of some of the first pad portionsPAD1 may include the first to third electrodes EL1, EL2, and EL3vertically adjacent to each other. In each of some of the first padportions PAD1, the sidewall of the second electrode EL2 corresponding tothe uppermost electrode may be horizontally spaced apart from thesidewall of the third electrode EL3 corresponding to the lowermostelectrode, and the sidewall of the first electrode EL1 may be verticallyaligned with the sidewall of the second electrode EL2 corresponding tothe uppermost electrode, as illustrated in FIG. 17. In exampleembodiments, the second distance D2 between the sidewalls of the secondand third electrodes EL2 and EL3 may be less than a half of the firstdistance D1 between the ends of the top surfaces of the first padportions PAD1.

Likewise, in each of some of the second pad portions PAD2, the sidewallof the first electrode EL1 corresponding to the uppermost electrode maybe horizontally spaced apart from the sidewall of the second electrodeEL2 corresponding to the lowermost electrode, and the sidewall of thethird electrode EL3 may be vertically aligned with the sidewall of thefirst electrode EL1 corresponding to the uppermost electrode.

FIG. 18 is a cross-sectional view illustrating a 3D semiconductor deviceaccording to example embodiments of the inventive concepts, and FIG. 19is an enlarged view of a portion ‘A’ of FIG. 18. In the presentembodiment, the descriptions of the same elements or technical featuresas in the embodiment of FIGS. 12 and 13 will be omitted or mentionedonly briefly for the purpose of ease and convenience in explanation.

Referring to FIGS. 18 and 19, each of some of the first pad portionsPAD1 may include the first to third electrodes ELL EL2, and EL3vertically adjacent to each other. In each of some of the first padportions PAD1, the sidewall of the second electrode EL2 corresponding tothe uppermost electrode may be horizontally spaced apart from thesidewall of the third electrode EL3 corresponding to the lowermostelectrode, and the sidewall of the first electrode EL1 may be verticallyaligned with the sidewall of the third electrode EL3 corresponding tothe lowermost electrode, as illustrated in FIG. 19. In exampleembodiments, the second distance D2 between the sidewalls of the secondand third electrodes EL2 and EL3 may be smaller than a half of the firstdistance D1 between the ends of the top surfaces of the first padportions PAD1.

Likewise, in each of some of the second pad portions PAD2, the sidewallof the first electrode EL1 corresponding to the uppermost electrode maybe horizontally spaced apart from the sidewall of the second electrodeEL2 corresponding to the lowermost electrode, and the sidewall of thethird electrode EL3 may be vertically aligned with the sidewall of thesecond electrode EL2 corresponding to the lowermost electrode.

FIGS. 20 and 21 are cross-sectional views illustrating 3D semiconductordevices according to example embodiments of the inventive concepts.Hereinafter, the descriptions of the same elements or technical featuresas in the embodiment of FIGS. 12 and 13 will be omitted or mentionedonly briefly for the purpose of ease and convenience in explanation.

Referring to FIG. 20, the stack structure ST may include first padportions PAD1 disposed at positions horizontally and verticallydifferent from each other in the first connection region CNR1. Inexample embodiments, one or some of the first pad portions PAD1 may havea first vertical thickness, and another or others of the first padportions PAD1 may have a second vertical thickness. For example, thenumber of electrodes included in at least one of the first pad portionsPAD1 may be different from the number of electrodes included in at leastanother of the first pad portions PAD1.

In example embodiments, the first pad portions PAD1 may include firstpads PAD1 a and second pads PAD1 b, as illustrated in FIG. 20. Each ofthe first pads PAD1 a may have one electrode, and each of the secondpads PAD1 b may have a plurality of electrodes sequentially stacked. Inexample embodiments, the first pad PAD1 a may be disposed between thesecond pads PAD1 b vertically adjacent to each other in the firstconnection region CNR1. In each of the second pads PAD1 b, a sidewall ofthe uppermost electrode may be horizontally spaced apart from a sidewallof the lowermost electrode. In example embodiments, a horizontaldistance between sidewalls of the uppermost and lowermost electrodes maybe less than a half of a horizontal distance between ends of topsurfaces of the first pad portions PAD1 adjacent to each other.

In addition, the stack structure ST may include second pad portions PAD2disposed at positions horizontally and vertically different from eachother in the second connection region CNR2. Like the first pad portionsPAD1, the second pad portions PAD2 may have vertical thicknessesdifferent from each other. In other words, the second pad portions PAD2may include first pads PAD2 a of which each has one electrode, andsecond pads PAD2 b of which each has a plurality of electrodessequentially stacked. In example embodiments, the first pad PAD2 a maybe disposed between the second pads PAD2 b vertically adjacent to eachother in the second connection region CNR2.

Referring to FIG. 21, vertical thicknesses of the first pad portionsPAD1 of the first connection region CNR1 may be different from those ofthe second pad portions PAD2 of the second connection region CNR2. Inaddition, the first pad portions PAD1 of the first connection regionCNR1 may include first and second pads PAD1 a and PAD1 b of which thevertical thicknesses are different from each other. In exampleembodiments, the first pad PAD1 a may have end portions of twoelectrodes sequentially stacked, and the second pad PAD1 b may have endportions of three electrodes sequentially stacked. In each of the firstand second pads PAD1 a and PAD1 b, the horizontal distance between thesidewalls of the uppermost and lowermost electrodes may be less than ahalf of the horizontal distance between the ends of the top surfaces ofthe first pad portions PAD1.

The second pad portions PAD2 of the second connection region CNR2 mayinclude first and second pads PAD2 a and PAD2 b of which the verticalthicknesses are different from each other. In example embodiments, thefirst pad PAD2 a may have an end portion of one electrode, and thesecond pad PAD2 b may have end portions of two electrodes sequentiallystacked. A horizontal distance between sidewalls of the electrodesstacked in the second pad PAD2 b may be less than a half of a horizontaldistance between ends of top surfaces of the second pad portions PAD2adjacent to each other.

FIGS. 22 and 23 are cross-sectional views illustrating 3D semiconductordevices according to example embodiments of the inventive concepts. Inthe present example embodiment, the descriptions of the same elements ortechnical features as in the embodiment of FIG. 8 will be omitted ormentioned only briefly for the purpose of ease and convenience inexplanation.

Referring to FIGS. 22 and 23, a stack structure ST may include aplurality of stacks stacked on the substrate 10, and lengths of thestacks may be sequentially reduced as a distance from the substrate 10increases. Thus, the stack structure ST may have stepwise structures inthe first and second connection regions CNR1 and CNR2.

In detail, the stack structure ST may include first pad portions PAD1,which are disposed at positions horizontally and vertically differentfrom each other in the first connection region CNR1. In addition, thestack structure ST may further include second pad portions PAD2, whichare disposed at positions horizontally and vertically different fromeach other in the second connection region CNR2.

In example embodiments, each of the stacks STR may include first,second, third, and fourth electrodes EL1, EL2, EL3, and EL4 sequentiallystacked. Each of the pad portions PAD may include end portions of thefirst to fourth electrodes EL1, EL2, EL3, and EL4 vertically adjacent toeach other. Each of the second pad portions PAD2 may include endportions of the first to fourth electrodes EL1, EL2, EL3, and EL4vertically adjacent to each other. In each of the first pad portionsPAD1, the uppermost electrode may be the fourth electrode EL4. In eachof the second pad portions PAD2, the uppermost electrode may be thefirst electrode EL1.

In example embodiments, ends of top surfaces of the first pad portionsPAD1 may be horizontally spaced apart from each other by a firstdistance D1. In each of the first pad portions PAD1, sidewalls of thelowermost and uppermost electrodes may be horizontally spaced apart fromeach other by a second distance D2. The second distance D2 may be lessthan a half of the first distance D1. The second pad portions PAD2 maybe similar to the first pad portions PAD.

In each of the first pad portions PAD1, the sidewall of the fourthelectrode EL4 corresponding to the uppermost electrode may behorizontally spaced apart from the sidewall of the first electrode EL1corresponding to the lowermost electrode by the second distance D2. Inaddition, in each of the first pad portions PAD1, sidewalls of thesecond and third electrodes EL2 and EL3 may be horizontally spaced apartfrom each other between the sidewalls of the first and fourth electrodesEL1 and EL4, as illustrated in FIG. 22. Alternatively, in each of thefirst pad portions PAD1, the sidewall of the second electrode EL2 may behorizontally spaced apart from the sidewalls of the first and thirdelectrodes EL1 and EL3, and the sidewall of the third electrode EL3 maybe vertically aligned with the sidewall of the fourth electrode EL4, asillustrated in FIG. 23. In addition, the positions of the sidewalls ofthe second and third electrodes EL2 and EL3 of the first pad portionPAD1 may be variously modified as described with reference to FIGS. 4 to7.

Each of the first pad portions PAD1 may have a stepwise sidewall profileby the first to fourth electrodes EL1 to EL4. In other words, the stackstructure ST may have a sidewall profile of a first stepwise structureby the first pad portions PAD1, and each of the first pad portions PAD1may have a sidewall profile of a second stepwise structure by the firstto fourth electrodes EL1 to EL4. In example embodiments, the firststepwise structure may have a first inclination angle (see θ1 of FIG. 3)smaller than 90 degrees, and the second stepwise structure may have asecond inclination angle (see θ2 of FIG. 3) which is greater than thefirst inclination angle (see θ1 of FIG. 3) and smaller than 90 degrees.In addition, the stack structure ST may also have the sidewall profilesof the first and second stepwise structures in the second connectionregion CNR2.

Hereinafter, a method of forming a stack structure of a 3D semiconductordevice according to example embodiments of the inventive concepts willbe described with reference to FIGS. 24 to 28.

FIGS. 24 to 28 are cross-sectional views illustrating an example methodof forming a stack structure of a 3D semiconductor device according toexample embodiments of the inventive concepts.

Referring to FIG. 24, a thin layer structure may be formed on asubstrate 10 including a cell array region CAR and a connection regionCNR. The thin layer structure may include a plurality of stacks STRvertically stacked on the substrate 10, and each of the stacks STR mayinclude a plurality of horizontal layers HL and a plurality ofinsulating layers ILD that are alternately stacked. In exampleembodiments, each of the stacks STR may include two horizontal layersHL.

In example embodiments, the thin layer structure may be patterned toform a stack structure ST having stepwise shape on the substrate 10 ofthe connection region CNR. In other words, forming the stack structureST may include repeatedly performing an etching process on the thinlayer structure a plurality of times.

In example embodiments, the process of forming the stack structure STmay include pad etching processes for forming pad portions of the stackstructure ST and a sub-etching process for reducing a gradient of asidewall profile of each of the pad portions with respect to a topsurface of the substrate 10. The pad etching process and the sub-etchingprocess may be alternately and repeatedly performed.

In example embodiments, as illustrated in FIG. 24, a mask pattern MP1covering the cell array region CAR and a portion of the connectionregion CNR may be formed on the thin layer structure, and the padetching process may be performed on the thin layer structure using themask pattern MP1 as an etch mask. At this time, the pad etching processmay etch a plurality of the horizontal layers HL. In exampleembodiments, an etch depth of the pad etching process may correspond toa vertical pitch of the pad portions. For example, the etch depth of thepad etching process may be about twice a vertical pitch of thehorizontal layers HL.

Next, referring to FIG. 25, the mask pattern MP1 may be etched such thata sidewall of the mask pattern MP1 is laterally moved by the seconddistance smaller than the half of the first distance, thereby forming asub-mask pattern MP2. The sub-etching process may be performed on thethin layer structure using the sub-mask pattern MP2 as an etch mask.Here, an etch depth of the sub-etching process may be substantiallyequal to the vertical pitch of the horizontal layers HL.

After the sub-etching process, the sub-mask pattern MP2 may be etchedsuch that a sidewall of the sub-mask pattern MP2 is moved by the firstdistance, thereby forming a reduced mask pattern MP1. Next, the padetching process may be performed again on the thin layer structure usingthe reduced mask pattern MP1 as an etch mask.

Because the pad etching process and the sub-etching process arealternately and repeatedly performed as described above, the stackstructure ST including the pad portions may be formed as illustrated inFIG. 26. The pad portions may be disposed at positions horizontally andvertically different from each other on the substrate 10 in theconnection region CNR. As described above, the stack structure ST mayhave the first stepwise structure having the first inclination angle θ1realized by the pad portions and the second stepwise structure havingthe second inclination angle θ2 realized by the horizontal layers HL ofeach of the pad portions.

Meanwhile, referring to FIGS. 27 and 28, the pad portions having thesidewall profile of the second stepwise structure may be formed byrepeatedly performing the pad etching process a plurality of times. Theetch depth of the pad etching process may be equal to or greater thantwice the vertical pitch of the horizontal layers HL. In exampleembodiments, the pad etching process using the mask pattern MP1 as anetch mask and the process of laterally moving the sidewall of the maskpattern MP1 by the first distance D1 may be alternately and repeatedlyperformed.

In detail, when a plurality of the horizontal layers HL are etchedduring the pad etching process using the mask pattern MP1 as an etchmask, an etch selectivity with respect to the lowermost horizontal layerHL of each of the stacks STR may be reduced as the number of thehorizontal layers HL increases. As a result, positions of sidewalls ofthe stacked horizontal layers HL may be different from each other andthe sidewalls of the horizontal layers HL exposed by the pad etchingprocess may be disposed at positions horizontally spaced apart from eachother or may be inclined as illustrated in FIG. 28.

FIG. 29 is a schematic block diagram illustrating a 3D semiconductormemory device according to example embodiments of the inventiveconcepts.

Referring to FIG. 29, a semiconductor memory device may include a cellarray region CAR and a peripheral circuit region. The peripheral circuitregion may include row decoder regions ROW DCR, a page buffer regionPBR, and a column decoder region COL DCR. In addition, a connectionregion CNR may be disposed between the cell array region CAR and the rowdecoder region ROW DCR.

A memory cell array may be disposed in the cell array region CAR. Thememory cell array may include a plurality of memory cells threedimensionally arranged. The memory cell array may include the pluralityof memory cells, a plurality of word lines, and a plurality of bitlines. The word lines and the bit lines may be electrically connected tothe memory cells.

A row decoder for selecting the word lines of the memory cell array maybe disposed in the row decoder region ROW DCR. An interconnectionstructure for electrically connecting the memory cell array to the rowdecoder may be disposed in the connection region CNR. In response toaddress signals, the row decoder may select one among memory blocks ofthe memory cell array and may select one among the word lines of theselected memory block. The row decoder may respectively provide a firstword line voltage and second word line voltages generated from a voltagegenerating circuit (not shown) to the selected word line and unselectedword lines in response to a control signal of a control circuit (notshown).

A page buffer for sensing data stored in the memory cells may bedisposed in the page buffer region PBR. According to an exampleoperation mode, the page buffer may temporarily store data to be storedin the memory cells or may sense data stored in the memory cells. Thepage buffer may operate as a write driver circuit in a program operationmode and may operate as a sense amplifier circuit in a read operationmode.

A column decoder connected to the bit lines of the memory cell array maybe disposed in the column decoder region COL DCR. The column decoder mayprovide a data transmission path between the page buffer and an externaldevice (e.g., a memory controller).

FIG. 30 is a plan view illustrating a 3D semiconductor memory deviceaccording to example embodiments of the inventive concepts. FIG. 31 is across-sectional view taken along a line I-I′ of FIG. 30 to illustrate a3D semiconductor memory device according to some embodiments of theinventive concepts.

Referring to FIGS. 30 and 31, a substrate 10 may include a cell arrayregion CAR and a connection region CNR. The substrate 10 may be a bulksilicon substrate, a silicon-on-insulator (SOI) substrate, a germaniumsubstrate, a germanium-on-insulator (GOI) substrate, a silicon-germaniumsubstrate, or a substrate having an epitaxial thin layer obtained byperforming a selective epitaxial growth (SEG) process, for example. Thesubstrate 10 may be formed of a semiconductor material. For example, thesubstrate 10 may include at least one of silicon (Si), germanium (Ge),silicon-germanium (SiGe), gallium-arsenic (GaAs), indium-gallium-arsenic(InGaAs), or aluminum-gallium-arsenic (AlGaAs), for example.

Stack structures ST may extend in parallel to each other along a firstdirection D1 on the substrate 10 and may be spaced apart from each otherin a second direction D2. Each of the stack structures ST may includeelectrodes EL vertically stacked on the substrate 10 and insulatinglayers ILD disposed between the electrodes EL. In example embodiments,each of the stack structures ST may include first and second electrodesEL1 and EL2 alternately and repeatedly stacked. Thicknesses of theinsulating layers of the stack structure ST may be varied according tocharacteristics of the semiconductor memory device. In exampleembodiments, a thickness of the lowermost insulating layer ILD may beless than thicknesses of others of the insulating layers ILD, and thethicknesses of the others of the insulating layers ILD may besubstantially equal to each other. In example embodiments, one or someof the insulating layers ILD may be thicker than others of theinsulating layers ILD.

In example embodiments, the connection region CNR may include a firstconnection region CNR1 and a second connection region CNR2. In exampleembodiments, each of the stack structures ST may include first padportions PAD1 in the first connection region CNR1 and second padportions PAD2 in the second connection region CNR2. In exampleembodiments, each of the first and second pad portions PAD1 and PAD2 mayinclude end portions of the first and second electrodes EL1 and EL2vertically adjacent to each other.

The first pad portions PAD1 may be arranged along the first direction D1in the connection region CNR when viewed from a plan view. The secondpad portions PAD2 may be arranged along the first direction D1 andadjacent to the first pad portion PAD1 in the second direction D2 whenviewed from a plan view.

Ends of top surfaces of the first pad portions PAD1 adjacent to eachother may be spaced apart from each other by a first distance in alongitudinal direction of the stack structure ST (i.e., in the firstdirection D1). A vertical pitch of the first pad portions PAD1 may bechanged according to the number of the electrodes included in each ofthe first pad portions PAD1. The second pad portions PAD2 may be similarto the first pad portions PAD1.

A first contact plug PLG1 may be in contact with the uppermost electrodeof each of the first pad portions PAD1, and a second contact plug PLG2may be in contact with the uppermost electrode of each of the second padportions PAD2.

In example embodiments, in each of the first and second pad portionsPAD1 and PAD2, a sidewall of the lowermost electrode may be horizontallyspaced apart from a sidewall of the uppermost electrode. In addition,the sidewalls of the electrodes EL of each of the first and second padportions PAD1 and PAD2 may be horizontally spaced apart from each otherbetween the first contact plugs PLG1 adjacent to each other or betweenthe second contact plugs PLG2 adjacent to each other. A horizontaldistance between the sidewalls of the uppermost and lowermost electrodesof each of the first and second pad portions PAD1 and PAD2 may be lessthan a half of the first distance.

In example embodiments, vertical structures VS may penetrate the stackstructures ST so as to be electrically connected to the substrate 10 inthe cell array region CAR. The vertical structures VS may include asemiconductor material or a conductive material. The vertical structuresVS penetrating each of the stack structures ST may be arranged in a linein one direction (e.g., the first direction D1). Alternatively, thevertical structures VS penetrating each of the stack structures ST maybe arranged in a zigzag form in one direction (e.g., the first directionD1). In example embodiments, the vertical structures VS may include asemiconductor material. In example embodiments, bottom surfaces of thevertical structures VS may be disposed at a level between a top surfaceand a bottom surface of the substrate 10. A contact pad may be disposedon a top end of each of the vertical structures VS, and a bit linecontact plug BPLG may be connected to the contact pad.

In example embodiments, a data storage layer DS may be disposed betweenthe stack structure ST and the vertical structure VS. In exampleembodiments, the data storage layer DS may include a vertical insulatingpattern penetrating the stack structure ST and a horizontal insulatingpattern extending from between the vertical insulating pattern and eachof the electrodes EL onto top and bottom surfaces of each of theelectrodes EL.

In example embodiments, the 3D semiconductor device may be an NAND flashmemory device. For example, the data storage layer DS disposed betweenthe stack structure ST and the vertical structure VS may include atunnel insulating layer, a charge storage layer, and a blockinginsulating layer. Data stored in the data storage layer DS may bechanged using the Fowler-Nordheim tunneling induced by a difference involtage between the vertical structure VS including the semiconductormaterial and the electrode EL of the stack structure ST.

Each of common source regions CSR may be disposed in the substrate 10between the stack structures ST adjacent to each other. The commonsource regions CSR may extend in parallel to the stack structures STalong the first direction D1. The common source regions CSR may beformed by doping portions of the substrate 10 with dopants. Aconductivity type of the common source regions CSR may be different fromthat of the substrate 10. For example, the common source regions CSR mayinclude N-type dopants (e.g., arsenic (As) or phosphorus (P)).

A common source plug CSP may be connected to each of the common sourceregions CSR, and a sidewall insulating spacer SP may be disposed betweenthe common source plug CSP and the stack structures ST. In exampleembodiments, the common source plug CSP may have a substantially uniformupper width and may extend in the first direction D1.

An upper filling insulation layer 120 may be disposed on an entire topsurface of the substrate 10 to cover the plurality of stack structuresST. The upper filling insulation layer 120 may have a planarized topsurface, and a thickness of the upper filling insulation layer 120 maybecome progressively greater from the cell array region CAR into theconnection regions CNR. In other words, the upper filling insulationlayer 120 may cover the first and second pad portions PAD1 and PAD2 ofthe stack structure ST in the connection region CNR.

In example embodiments, as described in above embodiments, the stackstructure ST may have the sidewall profile of the first stepwisestructure having the first inclination angle (see θ1 of FIG. 3) andrealized by the first pad portions PAD1, and each of the first andsecond pad portions PAD1 and PAD2 may have the sidewall profile of thesecond stepwise structure having the second inclination angle (see θ2 ofFIG. 3) and realized by the vertically adjacent electrodes thereof. Thesecond inclination angle (see θ2 of FIG. 3) may be greater than thefirst inclination angle (see θ1 of FIG. 3) and smaller than 90 degrees.As a result, even though the number of the electrodes of each of thefirst and second pad portions PAD1 and PAD2 increases, the upper fillinginsulation layer 120 may easily fill the stepped region between thefirst pad portions PAD1 adjacent to each other and/or between the secondpad portions PAD2 adjacent to each other.

A capping insulating layer 125 may be disposed on the upper insulatinglayer 120, and bit lines BL may be disposed on the capping insulatinglayer 125. The bit lines BL may extend in the second direction D2 tointersect the stack structures ST. The bit lines BL may be electricallyconnected to the vertical structures VS through the bit line contactplugs BPLG. In addition, first conductive lines CL1 and secondconductive lines CL2 may be disposed on the capping insulating layer125. The first conductive lines CL1 may be respectively connected to thefirst contact plugs PLG1, and the second conductive lines CL2 may berespectively connected to the second contact plugs PLG2.

FIG. 32 is a schematic block diagram illustrating a 3D semiconductormemory device according to example embodiments of the inventiveconcepts.

Referring to FIG. 32, a 3D semiconductor memory device according toexample embodiments may include a peripheral logic structure PS and acell array structure CS stacked on the peripheral logic structure PS. Inother words, the cell array structure CS may overlap with the peripherallogic structure PS when viewed from a plan view.

In example embodiments, the peripheral logic structure PS may includerow and column decoders, a page buffer, and control circuits. The cellarray structure CS may include a plurality of memory blocks BLK1 toBLKn, each of which corresponds to a data erase unit. The memory blocksBLK1 to BLKn may include structures that are disposed on a plane definedby first and second directions D1 and D2 and are stacked along a thirddirection D3. Each of the memory blocks BLK1 to BLKn may include amemory cell array having a three-dimensional structure or a verticalstructure. The memory cell array may include a plurality of memory cellsthree-dimensionally arranged, a plurality of word lines, and a pluralityof bit lines. The word lines and the bit lines may be electricallyconnected to the memory cells.

FIG. 33 is a cross-sectional view illustrating the 3D semiconductormemory device according to example embodiments of the inventiveconcepts, which is described with reference to FIG. 32. Hereinafter, thedescriptions of the same technical features as in the above embodimentswill be omitted or mentioned only briefly for the purpose of ease andconvenience in explanation.

Referring to FIG. 33, a peripheral logic structure PS and a cell arraystructure CS may be sequentially stacked on a semiconductor substrate10. In other words, the peripheral logic structure PS may be disposedbetween the semiconductor substrate 10 and the cell array structure CSwhen viewed from a cross-sectional view and the cell array structure CSmay overlap with the peripheral logic structure PS when viewed from aplan view.

The semiconductor substrate 10 may be a bulk silicon substrate, asilicon-on-insulator (SOI) substrate, a germanium substrate, agermanium-on-insulator (GOI) substrate, a silicon-germanium substrate,or a substrate having an epitaxial thin layer obtained by performing aselective epitaxial growth (SEG) process.

The peripheral logic structure PS may include row and column decoders, apage buffer, and control circuits. In other words, the peripheral logicstructure PS may include NMOS and PMOS transistors, a resistor, and acapacitor which are electrically connected to the cell array structureCS. The peripheral logic structure PS may be formed on an entire topsurface of the semiconductor substrate 10. In addition, thesemiconductor substrate 10 may include an N-well region NW doped withN-type dopants and a P-well region PW doped with P-type dopants. Activeregions ACT may be defined in the N-well region NW and P-well region PWby a device isolation layer 11.

The peripheral logic structure PS may include peripheral gate electrodesPG, source and drain dopant regions at both sides of each of theperipheral gate electrodes PG, peripheral circuit interconnections ICL,and a lower filling insulation layer 90 covering the peripheralcircuits. In detail, PMOS transistors may be formed on the N-well regionNW, and NMOS transistors may be formed on the P-well region PW. Theperipheral circuit interconnections ICL may be electrically connected tothe peripheral circuits through peripheral circuit plugs CP. Forexample, the peripheral circuit plugs CP and the peripheral circuitinterconnections ICL may be electrically connected to the NMOS and PMOStransistors.

The lower filling insulation layer 90 may cover the peripheral circuits,the peripheral circuit plugs CP, and the peripheral circuitinterconnections ICL. The lower filling insulation layer 90 may includea plurality of stacked insulating layers.

The cell array structure CS may be disposed on the lower fillinginsulation layer 90 and may include a horizontal semiconductor layer100, stack structures ST, and vertical structures VS.

The horizontal semiconductor layer 100 may be formed on a top surface ofthe lower filling insulation layer 90 covering the peripheral circuits.In other words, a bottom surface of the horizontal semiconductor layer100 may be in contact with the lower filling insulation layer 90. Thehorizontal semiconductor layer 100 may include a cell array region CARand a connection region adjacent to the cell array region CAR, asdescribed with reference to FIG. 1.

The horizontal semiconductor layer 100 may be formed of a semiconductormaterial. For example, the horizontal semiconductor layer 100 mayinclude at least one of silicon (Si), germanium (Ge), silicon-germanium(SiGe), gallium-arsenic (GaAs), indium-gallium-arsenic (InGaAs), oraluminum-gallium-arsenic (AlGaAs). The horizontal semiconductor layer100 may include a semiconductor material doped with dopants of a firstconductivity type and/or an intrinsic semiconductor material not dopedwith dopants. In addition, the horizontal semiconductor layer 100 mayhave a crystal structure including at least one of a single-crystallinestructure, an amorphous structure, or a poly-crystalline structure.

The stack structures ST may extend in parallel to each other along afirst direction D1 on horizontal semiconductor layer 100 and may bespaced apart from each other in a second direction D2, as described withreference to FIG. 30. Each of the stack structures ST may includeelectrodes EL vertically stacked on the horizontal semiconductor layer100 and insulating layers ILD disposed between the electrodes EL.

Each of the stack structures ST may have the stepwise structure forelectrically connecting the electrodes EL to the peripheral logicstructure PS in the connection region CNR, as described above. In otherwords, each of the stack structures ST may include pad portions disposedat positions vertically and horizontally different from each other inthe connection region CNR, and each of the pad portions may include endportions of a plurality of the electrodes sequentially stacked.

An upper filling insulation layer 120 may be disposed on the horizontalsemiconductor layer 100 to cover the end portions of the electrodesconstituting the pad portions. In addition, a capping insulating layer125 may cover the stack structures ST and the upper filling insulationlayer 120. Furthermore, bit lines BL may be disposed on the cappinginsulating layer 125 and may extend in the second direction D2 tointersect the stack structures ST. The bit lines BL may be electricallyconnected to the vertical structures VS through the bit line contactplugs BPLG.

The vertical structures VS may penetrate the stack structures ST so asto be electrically connected to the horizontal semiconductor layer 100.Each of the vertical structures VS may include a semiconductor patternelectrically connected to the horizontal semiconductor layer 100.

A data storage layer DS may be disposed between the stack structure STand the vertical structure VS.

Each of common source regions (not shown) may be disposed in thehorizontal semiconductor layer 100 between the stack structures STadjacent to each other. The common source regions may extend in parallelto the stack structures ST along the first direction D1. The commonsource regions may be formed by doping portions of the horizontalsemiconductor layer 100 with dopants of which a conductivity type isopposite to that of the horizontal semiconductor layer 100.

An interconnection structure for electrically connecting the cell arraystructure CS to the peripheral logic structure PS may be disposed on endportions of the stack structures ST, which have the stepwise structures.The upper filling insulation layer 120 covering the end portions of thestack structures ST may be disposed on the horizontal semiconductorlayer 100. The interconnection structure may include contact plugs PLGpenetrating the upper filling insulation layer 120 so as to be connectedto the end portions of the electrodes EL and conductive lines CLdisposed on the upper filling insulation layer 120 so as to be connectedto the contact plugs PLG. Vertical lengths of the contact plugs PLG maybe sequentially reduced as a horizontal distance from the cell arrayregion CAR decreases.

Pickup contact plugs PPLG may penetrate the upper filling insulationlayer 120 so as to be connected to pickup regions (not shown) formed inthe horizontal semiconductor layer 100. The pickup regions may includedopants of which a conductivity type is the same as that of thehorizontal semiconductor layer 100. In example embodiments, a dopantconcentration of the pickup region may be higher than that of thehorizontal semiconductor layer 100.

Top surfaces of the pickup contact plugs PPLG may be substantiallycoplanar with top surfaces of the contact plugs PLG. The pickup contactplug PPLG may be electrically connected to the peripheral logicstructure PS through a well conductive line PCL and a connection plugCPLG.

The connection plug CPLG may electrically connect the cell arraystructure CS to the peripheral logic structure PS. The connection plugCPLG may penetrate the upper filling insulation layer 120 and thehorizontal semiconductor layer 100 so as to be connected to theperipheral circuit interconnection ICL of the peripheral logic structurePS.

As the height of the stack structure including vertically stackedelectrodes increases, the number of the electrodes included in each padportion of the stack structure may increase. However, according toexample embodiments of the inventive concepts, each of the pad portionsmay have the sidewall profile of the second stepwise structure definedby the electrodes included in each of the pad portions. Thus, eventhough a height difference between the pad portions increases, thefilling insulation layer may easily fill the stepped region definedbetween the pad portions vertically adjacent to each other.

While the inventive concepts have been described with reference toexample embodiments, it will be apparent to those skilled in the artthat various changes and modifications may be made without departingfrom the spirits and scopes of the inventive concepts. Therefore, itshould be understood that the above embodiments are not limiting, butillustrative. Thus, the scopes of the inventive concepts are to bedetermined by the broadest permissible interpretation of the followingclaims and their equivalents, and shall not be restricted or limited bythe foregoing description.

What is claimed is:
 1. A three-dimensional (3D) semiconductor devicecomprising: a substrate including a cell array region and a connectionregion; a stack structure including a plurality of stacks verticallystacked on the substrate, each of the stacks having a pad portiondisposed in the connection region; and contact plugs connected to thepad portions of the stacks, respectively, wherein each of the padportions of the stacks includes a plurality of electrodes verticallystacked, and wherein, in at least one of the pad portions of the stacks,sidewalls of the electrodes are horizontally spaced apart from eachother between the contact plugs adjacent to each other.
 2. The 3Dsemiconductor device of claim 1, wherein ends of top surfaces of the padportions of the stacks are horizontally spaced apart from each other bya first distance, wherein, in the at least one of the pad portions ofthe stacks, a sidewall of an uppermost electrode is horizontally spacedapart from a sidewall of a lowermost electrode by a second distance, andwherein the second distance is less than a half of the first distance.3. The 3D semiconductor device of claim 2, wherein each of the contactplugs has a width greater than the second distance.
 4. The 3Dsemiconductor device of claim 2, wherein the pad portions include firstpad portions and second pad portions, wherein a number of the electrodesincluded in each of the second pad portions is less than a number of theelectrodes included in each of the first pad portions, and wherein, inthe first or second pad portion, a sidewall of an uppermost electrode ishorizontally spaced apart from a sidewall of a lowermost electrode bythe second distance.
 5. The 3D semiconductor device of claim 1, wherein,in another of the pad portions of the stacks, sidewalls of theelectrodes are vertically aligned with each other.
 6. The 3Dsemiconductor device of claim 1, wherein the stack structure has asidewall profile of a first stepwise structure defined by the padportions of the stacks, wherein each of the pad portions of the stackshas a sidewall profile of a second stepwise structure defined by theelectrodes thereof, wherein the first stepwise structure has a firstinclination angle with respect to a top surface of the substrate,wherein the first inclination angle is smaller than 90 degrees, whereinthe second stepwise structure has a second inclination angle withrespect to the top surface of the substrate, and wherein the secondinclination angle is greater than the first inclination angle andsmaller than 90 degrees.
 7. The 3D semiconductor device of claim 1,further comprising: a plurality of vertical structures penetrating theplurality of stacks in the cell array region; and a data storage layerdisposed between the stack structure and each of the verticalstructures.
 8. A 3D semiconductor device, comprising: a substrateincluding a cell array region and a connection region; a stack structureincluding a plurality of stacks vertically stacked on the substrate,each of the stacks extending from the cell array region into theconnection region, wherein each subsequently higher stack extends alesser distance into the connection region than the stack below it; andeach stack includes a plurality of electrodes having sidewall and topsurfaces with an uppermost electrode extending into the connectionregion a lesser distance than any other electrode within the stack. 9.The 3D semiconductor device of claim 8, further comprising: a pluralityof vertical structures penetrating the stacks in the cell array region;and a data storage layer disposed between each of the verticalstructures and the stacks.
 10. The 3D semiconductor device of claim 9,wherein the device is a vertical NAND (VNAND) device.
 11. The 3Dsemiconductor device of claim 9, wherein the stacked structure includestwo stepwise structures, the two stepwise structures including a firststepwise structure defined by the steps of individual stacks within thestack structure and having a first angle with the substrate associatedwith it and a second stepwise structure defined by the steps ofindividual electrodes within individual stacks and having a second anglewith the substrate associated with it, and the second angle that isdifferent from the first angle.
 12. The 3D semiconductor device of claim9, further comprising: a filling insulation layer formed on thesubstrate to cover the stack structure; conductive lines formed on topof the filling insulation layer; and contact plugs connecting theconductive lines to pads associated electrodes within each stack.